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| Product Specification PE4306 Product Description The PE4306 is a high linearity, 5-bit RF Digital Step Attenuator (DSA) covering a 31 dB attenuation range in 1dB steps, and is pin compatible with the PE430x series. This 50-ohm RF DSA provides both parallel (latched or direct mode) and serial CMOS control interface, operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE4306 exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4 mm QFN footprint. The PE4306 is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram Switched Attenuator Array RF Input RF Output 50 RF Digital Attenuator 5-bit, 31 dB, DC - 4.0 GHz Features * Attenuation: 1 dB steps to 31 dB * Flexible parallel and serial programming interfaces * Latched or direct mode * Unique power-up state selection * Positive CMOS control logic * High attenuation accuracy and linearity over temperature and frequency * Very low power consumption * Single-supply operation * 50 impedance * Pin compatible with PE430x series * Packaged in a 20 Lead 4x4 mm QFN Figure 2. Package Type 4x4 mm 20-Lead QFN Parallel Control Serial Control Power-Up Control 5 3 Control Logic Interface 2 Table 1. Electrical Specifications @ +25C, VDD = 3.0 V Parameter Operation Frequency Insertion Loss 2 Test Conditions Frequency DC - 2.2 GHz Minimum DC 30 15 - Typical 1.5 34 52 20 - Maximum 4000 2.25 (0.3 + 3% of atten setting) (0.3 + 5% of atten setting) 1 Units MHz dB dB dB dBm dBm dB s Attenuation Accuracy 1 dB Compression3 Input IP31, 2 Return Loss Switching Speed Any Bit or Bit Combination DC 1.0 GHz 1.0 < 2.2 GHz 1 MHz - 2.2 GHz Two-tone inputs +18 dBm 1 MHz - 2.2 GHz DC - 2.2 GHz 50% control to 0.5 dB of final value Notes: 1. Device Linearity will begin to degrade below 1 MHz 2. See Max input rating in Table 3 & Figures on Pages 2 to 4 for data across frequency. 3. Note Absolute Maximum in Table 3. Document No. 70-0160-04 www.psemi.com (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE4306 Product Specification Typical Performance Data @ 25C, VDD = 3.0 V unless otherwise noted Figure 3. Insertion Loss Figure 4. Attenuation at Major steps 0 35 31 dB 30 -1 25 -2 Normalized Error (dB) Insertion Loss (dB) 20 16 dB 15 -3 insertion loss @ 25 C insertion loss @ -40 C insertion loss @ 85 C 10 8 dB 4 dB 2 dB 1 dB 0 500 1000 1500 2000 2500 3000 3500 4000 -4 5 -5 0 500 1000 1500 2000 2500 3000 3500 4000 0 Frequency (MHz) Frequency (MHz) Figure 5. Input Return Loss at Major Attenuation Steps 0 Figure 6. Output Return Loss at Major Attenuation Steps 0 -10 -10 -30 16 dB S22 (dB) -20 s11 (dB) -20 -30 -40 31 dB 31 dB -40 16 dB -50 0 500 1000 1500 2000 2500 3000 3500 4000 -50 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (MHz) Frequency (MHz) (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11 Document No. 70-0160-04 UltraCMOSTM RFIC Solutions PE4306 Product Specification Typical Performance Data @ 25C, VDD = 3.0 V unless otherwise noted Figure 7. Attenuation Error Vs. Frequency Figure 8. Attenuation Error Vs. Attenuation Setting at 10 MHz and 510 MHz 1.5 2 0 1 -2 Error (dB) Error (dB) 0.5 31 dB -4 0 -6 -0.5 -8 -1 10 MHz @ 25 C 510 MHz @ 25 C 10 MHz @ -40 C 510 MHz @ -40 C 10 MHz @ 85 C 510 MHz @ 85 C 0 5 10 15 20 25 30 35 -10 0 500 1000 1500 2000 2500 3000 3500 4000 -1.5 Frequency (MHz) Attenuation State (dB) Figure 9. Attenuation Error Vs. Attenuation Setting 1010 MHz and 1210 MHz 1.5 Figure 10. Attenuation Error Vs. Attenuation Setting at 1510 MHz and 2010 MHz 1.5 1 1 0.5 Error (dB) Error (dB) 0.5 0 0 -0.5 1210 MHZ @ 25 C 1210 MHz @ -40 C 1210 MHz @ 85 C 1010 MHz @ 25 C 1010 MHz @ -40 C 1010 MHz @ 85 C 0 5 10 15 20 25 30 35 -0.5 -1 -1 1510 MHz @ 25 C 2010 MHz @ 25 C 1510 MHz @ -40 C 2010 MHz @ -40 C 1510 MHz @ 85 C 2010 MHz @ 85 C 0 5 10 15 20 25 30 35 -1.5 -1.5 Attenuation State (dB) Attenuation State (dB) Note: Positive attenuation error indicates higher attenuation than target value Document No. 70-0160-04 www.psemi.com (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11 PE4306 Product Specification Typical Performance Data @ 25C, VDD = 3.0 V unless otherwise noted Figure 11. Attenuation Error vs. Attenuation Setting at 2010 MHz and 2510 MHz 1.5 Figure 12. 1 dB Compression vs. Frequency 40 1 35 0.5 Error (dB) 1 dB Compression (dBm) 0 30 0 dB 1 dB 2 dB 31 dB -0.5 -1 2210 MHz @ 25 C 2510 MHz @ 25 C 2210 MHz @ -40 C 2510 MHz @ -40 C 2210 MHz @ 85 C 2510 MHz @ 85 C 0 5 10 15 20 25 30 35 25 -1.5 20 1000 1500 2000 Frequency (MHz) 2500 3000 Attenuation State (dB) Figure 13. Input IP3 vs. Frequency 60 55 50 45 IP3 (dBm) 40 35 30 25 20 1000 1500 2000 Frequency (MHz) 2500 3000 0 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31 dB Note: Positive attenuation error indicates higher attenuation than target value (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11 Document No. 70-0160-04 UltraCMOSTM RFIC Solutions PE4306 Product Specification Figure 14. Pin Configuration (Top View) GND N/C C1 C2 C4 Table 3. Absolute Maximum Ratings Symbol VDD VI Parameter/Conditions Power supply voltage Voltage on any DC input Storage temperature range Input power (50) ESD voltage (Human Body Model) Min -0.3 -0.3 -65 Max 4.0 VDD+ 0.3 150 +30 500 Units V V C dBm V 20 19 18 17 16 C16 RF1 Data Clock LE 1 2 3 4 5 10 15 C8 RF2 P/S Vss/GND GND TST PIN VESD 20-lead QFN 4x4 mm Exposed Solder Pad 14 13 12 11 VDD VDD PUP1 PUP2 GND Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. 6 7 8 9 Table 2. Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Paddle Table 4. Operating Ranges Parameter Description Min 2.7 Pin Name C16 RF1 Data Clock LE VDD PUP1 PUP2 VDD GND GND Vss/GND P/S RF2 C8 C4 C2 GND C1 N/C GND Typ 3.0 Max 3.3 100 Units V A V Attenuation control bit, 16 dB (Note 4). RF port (Note 1). Serial interface data input (Note 4). Serial interface clock input. Latch Enable input (Note 2). Power supply pin. Power-up selection bit. Power-up selection bit. Power supply pin. Ground connection. Ground connection. Negative supply voltage or GND connection (Note 3) Parallel/Serial mode select. RF port (Note 1). Attenuation control bit, 8 dB. Attenuation control bit, 4 dB. Attenuation control bit, 2 dB. Ground connection. Attenuation control bit, 1 dB. No connect. Can be connected to any bias. Ground for proper operation VDD Power Supply Voltage IDD Power Supply Current Digital Input High Digital Input Low Digital Input Leakage Input Power Temperature range 0.7xVDD 0.3xVDD 1 +24 -40 85 V A dBm C Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Switching Frequency The PE4306 has a maximum 25 kHz switching rate. Resistor on Pin 1 & 3 A 10 k resistor on the inputs to Pin 1 & 3 (see Figure 16) will eliminate package resonance between the RF input pin and the two digital inputs. Specified attenuation error versus frequency performance is dependent upon this condition. (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 11 Notes: 1: Both RF ports must be held at 0 VDC or DC blocked with an external series capacitor. 2: Latch Enable (LE) has an internal 100 kresistor to VDD. 3: Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to VSS (-VDD) to bypass and disable internal negative voltage generator. 4. Place a 10 kresistor in series, as close to pin as possible to avoid frequency resonance. See "Resistor on Pin 1 & 3" paragraph Document No. 70-0160-04 www.psemi.com PE4306 Product Specification Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE4306. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel / Direct Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 18 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 18) to latch new attenuation state into device. For direct programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The stop bit (B0) of the data should always be low to prevent an unknown state in the device. The timing for this operation is defined by Figure 17 (Serial Interface Timing Diagram) and Table 8 (Serial Interface AC Characteristics). Power-up Control Settings The PE4306 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/ S=1), the five control bits and a stop bit are set to whatever data is present on the five parallel data inputs (C1 to C16). This allows any one of the 32 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/ S=0) with LE=0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in Table 6 (Power-Up Truth Table, Parallel Mode). Table 5. Truth Table P/S C16 0 0 0 0 0 0 0 0 0 0 0 0 1 1 C8 0 0 0 0 1 0 1 C4 0 0 0 1 0 0 1 C2 0 0 1 0 0 0 1 C1 Attenuation State 0 1 0 0 0 0 1 Reference Loss 1 dB 2 dB 4 dB 8 dB 16 dB 31 dB Table 6. Power-Up Truth Table, Parallel Interface Mode P/S 0 0 0 0 0 Note: Not all 32 possible combinations of C1-C16 are shown. LE 0 0 0 0 1 PUP2 0 0 1 1 X PUP1 0 1 0 1 X Attenuation State Reference Loss 8 dB 16 dB 31 dB Defined by C1-C16 Serial Interface The PE4306's serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. The latch is controlled by three CMOScompatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11 Note: Power up with LE=1 provides normal parallel operation with C1-C16, and PUP1 and PUP2 are not active. Document No. 70-0160-04 UltraCMOSTM RFIC Solutions PE4306 Product Specification Evaluation Kit The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE4306 DSA. J9 is used in conjunction with the supplied DC cable to supply VDD, GND, and -VDD. If use of the internal negative voltage generator is desired, then connect -VDD (black banana plug) to ground. If an external -VDD is desired, then apply -3V. J1 should be connected to the LPT1 port of a PC with the supplied control cable. The evaluation software is written to operate the DSA in serial mode, so switch 7 (P/S) on the DIP switch SW1 should be ON with all other switches off. Using the software, enable or disable each attenuation setting to the desired combined attenuation. The software automatically programs the DSA each time an attenuation state is enabled or disabled. To evaluate the power up options, first disconnect the control cable from the evaluation board. The control cable must be removed to prevent the PC port from biasing the control pins. During power up with P/S=1 high and LE=0 or P/ S=0 low and LE=1, the default power-up signal attenuation is set to the value present on the five control bits on the five parallel data inputs (C1 to C16). This allows any one of the 32 attenuation settings to be specified as the power-up state. J4 Figure 15. Evaluation Board Layout Peregrine Specification 101/0112 Figure 16. Evaluation Board Schematic Peregrine Specification 102/0144 C1 C2 C4 20 19 18 17 C2 C1 N/C During power up with P/S=0 high and LE=0, the control bits are automatically set to one of four possible values presented through the PUP interface. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in the Table 6. Pin 20 is open and can be connected to any bias. C16 1 Z=50 Ohm DATA CLK LE 1 10kohm 2 3 10 kohm 4 5 GND C4 16 C16 C8 15 14 13 12 11 C8 Z=50 Ohm PS 1 J5 RFin DATA CLK U1 QFN4X4 RFout PS VDD_D VNEG GND GND SMA SMA PUP1 LE PUP2 VDD PUP1 VCC Resistor on Pin 1 & 3 A 10 k resistor on the inputs to pins 1 & 3 (Figure 16) will eliminate package resonance between the RF input pin and the two digital inputs. Specified attenuation error versus frequency performance is dependent upon this condition. Document No. 70-0160-04 www.psemi.com 100 pF Note: Resistors on pins 1 and 3 are required and should be placed as close to the part as possible to avoid package resonance and meet error specifications over frequency. (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 11 PUP2 10 6 7 8 9 PE4306 Product Specification Figure 17. Serial Interface Timing Diagram LE Table 7. 5-Bit Attenuator Serial Programming Register Map B5 C16 B4 C8 B3 C4 B2 C2 B1 C1 B0 0 Clock MSB (first in) MSB LSB LSB (last in) Data tSDSUP tSDHLD tLESUP tLEPW Note: The stop bit (B0) must always be low to prevent the attenuator from entering an unknown state. Figure 18. Parallel Interface Timing Diagram LE Parallel Data C16:C1 tPDSUP tLEPW tPDHLD Table 8. Serial Interface AC Characteristics VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol fClk tClkH tClkL tLESUP tLEPW tSDSUP tSDHLD Table 9. Parallel Interface AC Characteristics VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol tLEPW tPDSUP tPDHLD Parameter Serial data clock frequency (Note 1) Serial clock HIGH time Serial clock LOW time LE set-up time after last clock falling edge LE minimum pulse width Serial data set-up time before clock rising edge Serial data hold time after clock falling edge Min Max 10 Unit MHz ns ns ns ns ns ns Parameter LE minimum pulse width Data set-up time before rising edge of LE Data hold time after falling edge of LE Min 10 10 10 Max Unit ns ns ns 30 30 10 30 10 10 Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11 Document No. 70-0160-04 UltraCMOSTM RFIC Solutions PE4306 Product Specification Figure 19. Package Drawing 4.00 INDEX AREA 2.00 X 2.00 -B2.00 2.00 0.25 C -A0.10 C 0.08 C 0.020 0.20 REF EXPOSED PAD & TERMINAL PADS SEATING PLANE 0.80 4.00 -C2.00 TYP 0.50 TYP 0.55 2.00 1.00 5 11 0.435 0.18 1.00 EXPOSED PAD 0.23 1 0.10 CAB 2.00 1 15 20 16 6 10 0.435 0.18 4.00 DETAIL A DETAIL A 2 1. Dimension applies to metallized terminal and is measured between 0.25 and 0.30 from terminal tip. 2. Coplanarity applies to the exposed heat sink slug as well as the terminals. 3. Dimensions are in millimeters. Document No. 70-0160-04 www.psemi.com (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 11 PE4306 Product Specification Figure 20. Marking Specifications 4306 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number Figure 21. Tape and Reel Drawing Table 10. Ordering Information Order Code 4306-00 4306-51 4306-52 Part Marking PE4306-EK 4306 4306 Description PE4306-20MLP 4x4mm-EK PE4306G-20MLP 4x4mm-75A PE4306G-20MLP 4x4mm-3000C Package Evaluation Kit Green 20-lead 4x4mm QFN Green 20-lead 4x4mm QFN Shipping Method 1 / Box 75 units / Tube 3000 units / T&R (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11 Document No. 70-0160-04 UltraCMOSTM RFIC Solutions PE4306 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Europe Peregrine Semiconductor Europe Batiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Space and Defense Products Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP and MultiSwitch are trademarks of Peregrine Semiconductor Corp. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0160-04 www.psemi.com (c)2003-2008 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 11 |
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